A NOR Flash Squeeze, a $3 Billion Opening: How Everspin Plans to Put MRAM Inside AI Servers, Satellites and Data Center Memory Tiers
By David Nakamura — AI & Data News
Design teams that long treated NOR flash as a commodity line item are now asking a different question first: what can we actually buy this quarter? That shift in procurement reality is what has moved magnetoresistive random-access memory (MRAM) out of its established industrial base and into discussions about AI servers, data center memory tiers and satellite systems. Everspin Technologies is trying to convert that discomfort into volume, and president and CEO Sanjeev Aggarwal set out the plan in an exclusive interview with EE Times.
His framing is less about inventing a new category than about working around the limits of the memory that is available today: “If you care for performance, I think that MRAM is the only solution we have,” he told EE Times.
The numbers behind the shortage pitch
Aggarwal said customers are weighing MRAM for performance and reliability, and also because some NOR flash products have become difficult to obtain. A TrendForce report estimated that NOR flash contract prices rose by a cumulative 100% to 120% in the first half of 2026. That report said AI-related demand absorbed much of the limited supply, listed NOR flash among the first products to face longer lead times and allocation, and noted that suppliers had not announced major capacity expansion.
The gap left by those shortages is the opening Aggarwal sizes at $3 billion in 2028 or 2029. He said Everspin has been developing a product for that market using TSMC's manufacturing process.
“Now people cannot buy NOR flash,” he said. “Most of the fabs in Asia have converted from NOR flash to DRAM. Much better profit margins. Then what is the alternative? MRAM is the only alternative for standalone or discrete products. And that is where they approach us.”
Relative pricing is doing much of the persuading. Aggarwal said MRAM previously cost about three times as much as NOR flash, but the gap narrowed to about 1.5 times as NOR flash prices rose under supply constraints. “If you are going to use two NOR flash chips, you might as well just use one MRAM and be more cost-effective,” he said.
A TrendForce chart dated June 2026 covers supply-demand conditions and pricing outlook for SLC NAND and NOR Flash in the second half of 2026.
How buyers and engineers are doing the math
The outcome depends on the application, including how many chips a design requires and which performance and reliability specifications it must satisfy. Aggarwal said Everspin's distributors had started requesting cross-reference information to help customers identify MRAM alternatives when particular NOR flash components were unavailable.
Four variables recur in those substitutions:
- the number of chips the design currently needs,
- performance and reliability specifications,
- temperature and operating-condition requirements, and
- read-write endurance.
Other non-volatile memory technologies can also be unsuitable for particular applications. In the products he described, Ferroelectric RAM (FRAM) has lower available densities, while non-volatile static random-access memory (NVSRAM) can present tradeoffs in reliability and operating conditions. Everspin specifies an operating temperature range of minus 40°C to 125°C for the parts Aggarwal discussed, and he cited reliability, SRAM- and DRAM-like performance, and read-write endurance as reasons customers select MRAM.
| Option | What the interview puts on the table | Limitation as stated |
|---|---|---|
| MRAM (Everspin parts discussed) | 20 to 30 nanoseconds access; reliability, endurance and SRAM- and DRAM-like performance; minus 40°C to 125°C | Densities currently reach one gigabit; price is about 1.5 times NOR flash |
| NOR flash | The incumbent for standalone or discrete products; previously far cheaper, at roughly a third of MRAM's earlier cost | Contract prices up a cumulative 100% to 120% in the first half of 2026, with longer lead times and allocation |
| FRAM | Another non-volatile option customers ask about | Lower available densities |
| NVSRAM | Another non-volatile option customers ask about | Tradeoffs in reliability and operating conditions |
Corporate baseline: revenue, guidance and the growth logic
According to its annual report filed with the U.S. Securities and SEC (SEC), Everspin reported revenue of $55.2 million for 2025, up 9.5% from $50.4 million in 2024. Aggarwal said he expects the company to double revenue over three to four years, with the NOR flash opportunity and demand from data centers, aerospace and defense, low-Earth-orbit (LEO) satellites, and industrial automation contributing to its growth ambitions.
CXL demonstration: MRAM as a tier, not a replacement
Everspin demonstrated MRAM modules combined with a Compute Express Link (CXL) controller at the Storage Networking Industry Association (SNIA) Developer Conference in Santa Clara, California. The setup created a pool of persistent memory accessible through CXL.mem, a protocol that allows a system to access memory over a CXL connection.
Aggarwal described the demonstration as a way to show how MRAM could function as an additional memory tier between dynamic random-access memory (DRAM), which serves as working memory, and NAND flash, which provides storage. By his account, DRAM operates on a timescale of nanoseconds, while NAND flash access can take hundreds of microseconds, and moving data between processing and slower storage can delay workloads.
“Our memory is 20 to 30 nanoseconds,” he said. “You can use it for storage as well as compute, reducing the gap between NAND storage and DRAM working memory.”
The proposed role is to hold data generated during AI processing before it is transferred to longer-term storage. Candidates he named include key-value (KV) caches, checkpoints, and data awaiting a write to storage. A KV cache retains information that an AI model reuses while generating a response; checkpoints allow a computing job to resume after a failure.
Everspin's densities currently reach one gigabit, but Aggarwal said devices could potentially be stacked to provide 8 Gb or 16 Gb; capacity remains a limitation. He argued the technology would not need to match NAND flash capacity if it held intermediate data only temporarily.
The company is also developing a roadmap for higher-density memory and newer interfaces. Aggarwal said Everspin has supplied IBM's FlashCore Modules and wants to expand its data center business with products that go beyond its existing DDR4 interface.
“Our demonstration of the CXL protocol with our existing DDR4 chip will start getting us some entry into the data center market,” he said. “And by the time we have a good foothold, we will have a 4-Gb DDR6 part ready to go right behind it.” Aggarwal estimated that this development would take about three years.
At the edge, he said, MRAM could reduce the need to transfer data between devices and central servers for processing, citing OpenMV as an example of an application in which Everspin has replaced SRAM and added MRAM for configuration.
On orbit: a boot-path design win in geosynchronous Earth orbit
For a geosynchronous Earth orbit (GEO) mission, Astro Digital selected Everspin's 64Mb PERSYST spin-transfer torque MRAM (STT-MRAM), part number EM064LXQADG13IS1T, as the primary fail-safe memory for the boot process on its Raven satellite bus earlier this year. Boot memory stores the code needed to start a spacecraft's electronics and support system recovery.
“What Astro Digital did recently was, they took our part and sent it into geosynchronous orbit,” Aggarwal said. “So, not low Earth, but they sent those to geosynchronous orbit.”
He said MRAM's radiation tolerance is useful in space, while adding that the surrounding silicon can still be vulnerable to radiation damage. In the satellite configuration he described, a backup memory provides an additional safeguard if the surrounding circuitry is affected.
Aggarwal also cited MRAM's write speed and reliability as advantages over NOR flash in satellite applications, saying the memory can be written almost three orders of magnitude faster than NOR flash and consumes less power in the applications he described. Everspin lists 64-Mb, 128-Mb, and 256-Mb capacities in its PERSYST family, which uses a quad serial peripheral interface (QSPI).
He gave a general example of how MRAM could reduce chip count in some applications, but noted that the comparison should not be read as a description of Astro Digital's actual satellite configuration.
AI server workloads under a signed framework
The company has signed a memorandum of understanding (MoU) with MaxLinear to evaluate MRAM alongside MaxLinear's storage compression, encryption, and hardware acceleration platform for AI servers. The evaluation targets a defined set of data-intensive workloads:
- metadata management,
- log data,
- write buffering,
- cache,
- and other data-intensive workloads.
The companies also plan technical validation and market development aimed at hyperscale cloud providers, AI infrastructure developers, and enterprise server customers, and the agreement includes potential longer-term manufacturing, supply, and commercialization opportunities.
Aggarwal said MaxLinear was the first target for the work because of its accelerator technology. “They have accelerators, so they were very interested in the technology,” he said. “We are working with them to find the first use case.”
Read with care: the MoU establishes an evaluation framework; it does not announce a finished product or a volume commitment.
Manufacturing expansion and the two-source plan
Everspin produces two main MRAM families: field-switched, or toggle, MRAM, and STT-MRAM. It manufactures toggle MRAM at its 8-inch facility in Chandler, Arizona. The portfolio ranges from 128 kilobits to 1 Gb, spanning several densities and interfaces. Aggarwal said the company had shipped more than 200 million units over 20 years, with only a handful of returns.
Earlier this year, the company signed an initial 10-year foundry services agreement with Microchip Technology to establish an 8-inch MRAM and tunnelling magnetoresistance (TMR) sensor manufacturing line at Microchip's Fab 4 facility in Gresham, Oregon. The agreement is intended to provide a second U.S. manufacturing source for toggle MRAM. The U.S. SEC filing stated that the first products are expected to ship in the second half of 2027.
“We signed a foundry services agreement with Microchip, which allows me to manufacture twice the amount of toggle MRAM that I could manufacture in Chandler,” Aggarwal said.
The agreement is also connected to a $40 million U.S. government contract awarded through Amentum Services, with Everspin acting as a subcontractor. Aggarwal said the work will qualify Everspin's process at Microchip and provide the government with access to the company's intellectual property and a second manufacturing line for future government products.
For STT-MRAM, Everspin has worked with GlobalFoundries on 12-inch wafers since 2016. It also plans to tape out a product using TSMC's 16-nm process, which Aggarwal said would diversify supply. The stated aim is two manufacturing sources for both product families: Chandler and Oregon for toggle MRAM, and GlobalFoundries and TSMC for STT-MRAM. Capacity was not currently a constraint, he said.
Competition exists in the commercial MRAM market. South Korean company Netsol, which uses Samsung Foundry, offers a 16-Mb product, Aggarwal said, and he expects a 1-Gb product from the competitor to reach the market in 2028 or 2029.
India: aerospace, automotive and rail on the distribution map
India is another potential market, particularly in aerospace and defense, electric vehicles, and railways. Aggarwal said he was seeking connections with the Defence Research and Development Organisation (DRDO), the Indian Space Research Organisation (ISRO), and Indian satellite companies.
He identified battery management systems and vehicle data recorders as possible applications, alongside flight control systems, and said Everspin is working to expand its Indian distribution network, exploring local partnerships including discussions with Indian distributors and possible outsourced semiconductor assembly and test (OSAT) arrangements.
Aggarwal also said the company was speaking with Indian automotive groups and exploring opportunities in rail, citing existing deployments in rail systems in Europe, Japan, and China, where memory stores operational data.
“We are always in discussions about these potential opportunities,” he said of Indian railway opportunities. “There is nothing that I can talk about openly, but obviously the conversations are ongoing.”
FAQ: what this means for infrastructure teams
Why has a NOR flash shortage become an AI infrastructure story?
Because the same demand surge is doing both jobs. The TrendForce estimate puts cumulative NOR flash contract price increases at 100% to 120% in the first half of 2026, attributes much of the tight supply to AI-related demand, and notes no announced major capacity expansion — which is why lead times and allocation arrived early for this product.
Is MRAM being pitched as a replacement for DRAM or NAND?
No. Aggarwal's positioning is a middle tier: DRAM at nanoseconds for working memory, NAND where access can take hundreds of microseconds for storage, and MRAM at 20 to 30 nanoseconds to hold intermediate AI data such as KV caches and checkpoints before it is written away.
How much capacity can today's parts carry?
Everspin's densities currently reach one gigabit, with devices potentially stacked to 8 Gb or 16 Gb. Aggarwal treats capacity as the open limitation, while arguing a temporary holding tier does not need NAND-level capacity.
Does the MaxLinear agreement mean a product exists?
It does not. The MoU sets an evaluation framework and plans technical validation and market development; there is no announced finished product or volume commitment.
Where would the parts be built?
Toggle MRAM is made at the 8-inch fab in Chandler, Arizona, with a second planned source at Microchip's Fab 4 in Gresham, Oregon, where first products are expected in the second half of 2027 per the U.S. SEC filing. STT-MRAM runs on GlobalFoundries 12-inch wafers since 2016, with a planned tape-out on TSMC's 16-nm process.
What to watch next
The common thread across the CXL demonstration, the GEO boot-memory design win, the MaxLinear evaluation and the second U.S. production line is a company trying to convert a component shortage into a permanent place in the memory hierarchy. Aggarwal expects demand to grow as manufacturing efficiencies reduce cost per bit. The measurable follow-ups are narrow: whether the 4-Gb DDR6 part arrives on the roughly three-year timeline he described, whether first shipments from Fab 4 land in the second half of 2027, whether a competitor's 1-Gb product does appear in 2028 or 2029, and whether customers who cross-reference to MRAM during the shortage keep the design once allocation pressure eases.