Two Transistors, No Capacitor: Inside the $5M Bet on Z2RAM as an AI Memory Alternative

Computer memory has been refined rather than rethought for a very long time, and that is precisely the assumption a U.S. startup is asking investors to challenge. Nagare Labs has closed a $5 million seed round led by Playground Global, the fund in which Kissinger participates, to push forward a storage cell it calls Z2RAM. The proposition is compact but sweeping: take the advantages of SRAM, DRAM and flash and aim for a memory that is at once high-density, fast and scalable — built on a cell of just two transistors rather than a dedicated capacitor.

The company traces back to the Georgia Institute of Technology, where co-founders Suman Datta and Shimeng Yu built their work on years of research into emerging memories, including ferroelectric and resistive random access technologies. The framing Kissinger has offered is that mainstream storage has not changed in any fundamental way over the past three decades — SRAM, DRAM and NAND flash still constitute the base of modern computing devices — while the rapid growth of AI compute demand is making the limits of that arrangement harder to ignore.

Where the Charge Lives Is the Real Change

Conventional DRAM rests on a one-transistor, one-capacitor cell. Data is expressed as charge held in that capacitor, and the charge leaks away over time, which forces periodic refresh. The read is destructive: sensing consumes the stored charge, so the value has to be written back.

SRAM approaches the problem from the other direction. A cell is usually formed by six transistors, which removes the need for periodic refreshing and makes reads very fast — the reason it is used for high-speed cache inside processors. The penalty is a large cell area and high manufacturing cost, which keep SRAM from scaling to the high densities reached by DRAM and NAND.

Z2RAM tries to find a new balance between the two. It uses two transistors per cell and abandons the separate capacitor used in traditional DRAM, instead preserving charge in the gate capacitance of the second transistor. According to Nagare Labs co-founder Suman Datta, that design enables non-destructive read: data can be sensed without draining the stored charge and therefore without a rewrite, which is expected to lower access latency and improve overall storage efficiency.

The Numbers Now on the Table

Technology	Cell structure	Read behavior	Density and role
SRAM	Typically six transistors per cell	No periodic refresh; very fast reads	Large cell area, high cost; used as processor cache
DRAM	One transistor paired with one capacitor	Destructive read; charge leaks, so data must be refreshed and rewritten	Scales to large, high-density capacity; a pillar of the last three decades
NAND flash	Vertically stacked layers — a concept Z2RAM plans to borrow	Forms part of the mainstream storage base	High-density expansion is its strength
Z2RAM (first-generation target)	Two transistors; the second transistor's gate capacitance holds the charge	Non-destructive read, no rewrite after sensing	Claimed more than 5x the storage density of SRAM, with bandwidth close to SRAM

Nagare Labs expects the first generation of Z2RAM to reach more than five times the storage density per unit area of conventional SRAM. The company offers a simple illustration: if a given area of SRAM delivers 64MB of capacity, the same area built with Z2RAM could theoretically rise to around 320MB while keeping bandwidth near SRAM levels.

Why AI Processor Designers Are the Customer to Watch

That combination matters for AI silicon. Today's accelerators lean heavily on HBM for bandwidth, but HBM requires complex stacked packaging, carries high manufacturing cost, and brings constraints on power and package area. At the other extreme, some processors dedicated to AI inference place large amounts of SRAM on-chip to minimize the latency of reaching external memory; because SRAM density is limited, chip designers must trade capacity against compute units within a fixed area.

The Nvidia Groq 3 LPU is a case in point: it uses substantial SRAM as on-chip storage, with roughly 500MB of SRAM per chip. Under Nagare Labs' technical assumptions, if Z2RAM achieves the expected 5x density, the same silicon area could hold several times more data. That could reduce the number of processors a large AI inference system needs and ease the pressure of shuttling data between chips.

Integration Plan: Oxide Semiconductor Stacked Above Logic

A second defining feature is the materials and assembly route. Z2RAM is built with oxide semiconductor material and is planned for direct integration above compute logic dies using 3D hybrid bonding. Rather than depending entirely on the traditional separation between memory chips and processors, the approach stacks a high-density memory layer close to the compute chip and shortens the distance data must travel. The design thinking shares some ground with AMD's 3D V-Cache, which adds extra SRAM cache stacked on a processor, except that Z2RAM is aiming for higher storage density.

On process, Nagare Labs also intends to borrow the vertical stacking idea from NAND flash, constructing multiple memory layers one above another. Instead of relying on the complex high-density packaging that HBM and LPDDR require, the company hopes to reach relatively simple multi-layer manufacturing through oxide semiconductor and back-end processing — a path that, if it succeeds, could lower the cost of large-capacity on-chip storage.

Five Things That Have to Go Right

1. Foundry capability. Z2RAM is still at a very early research stage. The $5 million seed round has just closed, and current results are largely laboratory prototypes rather than mature chip manufacturing. The company is seeking wafer fab partners able to provide R&D manufacturing, moving the technology out of a university cleanroom into larger-scale production validation.
2. Interface standards. Z2RAM must be connected to processors or AI accelerators through 3D hybrid bonding, yet the industry has not formed a unified interface standard suited to such a new memory. Georgia Tech researchers note that without mature standards, Nagare Labs may have to develop its own interface technology, adding complexity to product design and commercialization.
3. Material reliability. Oxide semiconductors have advantages in thermal stability and radiation resistance, but defects such as atomic vacancies can appear inside the material, affecting transistor threshold voltage; even a very small voltage shift can produce data errors in a storage cell.
4. Qualification. For memory products, reliability usually matters more than peak performance in the lab. Any new storage technology needs long validation of data retention, read/write endurance, temperature variation and manufacturing consistency before it can enter a commercial market.
5. Survival odds. The co-founders acknowledge that many memory startups have tried to challenge traditional DRAM and flash and ultimately failed: strong laboratory results do not guarantee passing the semiconductor industry's strict quality standards or entering the supply chains of existing computing systems.

The disclosed timeline is correspondingly long: working Z2RAM memory chip samples are targeted within the next four years, and the company is aiming for commercial shipments within the next ten years.

The Strategic Read: An Architecture Variable, Not a Short-Term Supply Fix

Kissinger's interest is inseparable from the memory bottleneck now shaping the AI industry. Training and inference for large language models require not only strong compute but a continuous flow of data into that compute; when processing speed far outstrips memory's ability to supply it, processors wait, and expensive compute sits underutilized.

HBM is the principal answer to AI accelerator bandwidth today, and it is not without flaws. Kissinger's view is that if Z2RAM can deliver its expected performance, it has the chance to offer a solution different from existing HBM in storage density, speed and power.

What it is not is a near-term remedy for the global shortage of DRAM and HBM supply. Even if engineering samples arrive in four years, large-scale commercialization remains a long way off. Current memory tightness is driven mainly by surging AI data center demand and by Samsung, SK Hynix and Micron shifting more capacity toward HBM and server memory products.

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Should Z2RAM eventually reach volume production, its significance is likely to be measured in architecture rather than in added supply of conventional memory chips. The promise is AI processors carrying far more high-speed storage inside the package, depending less on external memory bandwidth, and giving next-generation AI accelerators a new design option.

FAQ: What Readers Are Asking About Z2RAM

Is Z2RAM a shipping product?

No. Nagare Labs has just completed a $5 million seed round and its results so far are laboratory prototypes. It is looking for fab partners, targeting working samples within the next four years and commercial shipments within the next ten years.

Why two transistors instead of six transistors or one-transistor-plus-capacitor?

Because that cell count is where the trade-offs live. Six transistors give SRAM its speed but consume area; a single capacitor is what forces DRAM to refresh and to rewrite after a destructive read. Z2RAM keeps two transistors and reuses the second one's gate capacitance to hold charge, aiming for non-destructive reads at higher density.

Is it meant to replace HBM?

The company's claim is narrower than that headline: Kissinger argues Z2RAM could, if it meets expectations, provide a different answer from existing HBM on density, speed and power, while letting AI processors keep more fast storage on-chip and reduce reliance on external bandwidth.

Would it solve today's memory shortage?

No. The technology is too early to relieve current DRAM and HBM supply pressure, which stems largely from AI data center demand and from Samsung, SK Hynix and Micron redirecting capacity to HBM and server memory.

What would make the project fail?

Missing a unified interface standard for bonding this kind of memory to compute dies; atomic vacancy defects in oxide semiconductors shifting threshold voltage and corrupting data; failure to clear long-term reliability and manufacturing-consistency validation; and the industry's own history, in which many memory startups challenging DRAM and flash did not succeed.

Reporting by David Nakamura · AI & Data News (AIdataNewsGlobal) · Editorial contact: editorial@aidatanews.com