Inside Synaptics’ Multimodal Edge AI Push: Astra SR200 xMCU Specs, a Three-Version Line-Up and a Wider Coralboard Family
For teams shipping AI features into battery-powered hardware, the binding constraint is rarely the network architecture itself. It is the memory budget and the power envelope wrapped around that architecture. That was the problem Synaptics Inc. placed at the centre of its annual tech day, where the company introduced the Astra SR200 series as the opening product of a new microcontroller class it calls xMCU, and in the same session broadened the Coralboard family with a Coralboard SR development board alongside general availability of the Coralboard SL.
Considered together, the two announcements operate on three levels at once: silicon, toolchain and board-level access. The breakdown below follows that order, collects the headline numbers in tables, and closes with a FAQ for readers benchmarking the platform against a current product roadmap.
At a glance: six facts that frame the launch
- A new category label. Synaptics positions the xMCU as a microcontroller class built for multimodal edge AI — voice, vision, audio, motion and contextual sensing handled on-device instead of being offloaded to a gateway or the cloud.
- Memory close to the compute. The Astra SR200 series pairs up to 8 MB of SRAM with extensible, high-bandwidth, high-capacity custom DRAM that can scale to hundreds of megabytes as models and workloads require.
- The power argument. According to Synaptics, the design executes workloads at one-third the power of typical system DRAM, removing the need for external memory in most applications while using only a fraction of system power.
- A tiered line-up. The xMCU series is offered in three versions — SR210, SR230 and SR250 — that are pin-compatible and share a common hardware foundation and software development kit.
- Accelerator lineage. The SR200 Series runs on the Synaptics Torq AI engine, which integrates the Coral NPU from Google Research and is supported by an open-source MLIR/IREE compiler.
- Developer boards. The Coralboard SR development board is new; the Coralboard SL is now generally available through DigiKey, and the Synaptics Coralboard can be ordered from October 20, 2026.
Why memory, not raw compute, is the headline
The tiered architecture is the part of the pitch that most directly changes product design. The SRAM layer of up to 8 MB sits next to the compute domains, while the custom DRAM layer extends into hundreds of megabytes when a larger model demands it. Synaptics states that this memory executes workloads at one-third the power of typical system DRAM, which is the basis for its claim that most applications no longer need an external memory component.
That combination is what allows larger AI models and multimodal workloads to operate entirely on-device. The target list attached to the series follows the same logic: AI wearables, battery-powered sensing devices, connected cameras, streamers, and industrial vision and voice systems.
Core vectors: how the platform is presented
Synaptics describes the Astra SR200 series as organised around several core vectors that increase design flexibility: high-performance compute with extensible memory, transformer-ready AI acceleration, silicon-rooted security, multimodal integration, an ultra-low-power architecture with tiered domains, and an open-source software ecosystem.
Scalability is handled through the line-up itself. The xMCU series is offered in three versions, pin-compatible and built on a shared hardware foundation and SDK, so a design can move between compute tiers without a full re-layout.
| Version | Compute | Positioning | Workload emphasis |
|---|---|---|---|
| SR210 | 200 GOPS | power-optimized, always-on | voice and sensing |
| SR230 | 300 GOPS | mainstream multimodal devices | vision, display and optional audio |
| SR250 | 400 GOPS | premium edge applications | dual vision and display paths |
Astra SR200 xMCU (Source: Synaptics Inc.)
Compute engine, core pairing and the audio path
The SR200 Series uses the Synaptics Torq AI engine, a standards-based hardware architecture and unified developer experience that integrates the Coral NPU from Google Research. Synaptics said the engine is optimised for low-latency, high-efficiency execution of deep learning workloads, including CNN, transformer and fully connected networks, while the open-source MLIR/IREE compiler supports industry-standard frameworks and model formats.
On the processor side, the series claims the industry’s first pairing of the Arm Cortex-M85 and Cortex-M52. Scaling to 800 MHz, the high-performance core handles control, multimedia and burst-compute workloads; the efficiency core provides always-on sensor fusion, connectivity and low-power inference. An optional Cadence Tensilica HiFi 5 DSP is available for dedicated audio and acoustic ML processing, and an always-on domain manages voice activity detection, timekeeping and wake-up.
Security, peripherals and industrial I/O
Protection is built on a multi-layered security engine that combines hardware isolation, cryptographic acceleration, anti-tamper detection, device lifecycle management and secure boot. The series meets PSA Level 3 and CC EAL4+ certification targets, providing defence against software and physical attacks.
For flexibility, the platform offers a wide range of peripherals and connectivity, including high-speed octal SPI, SDIO and eMMC storage interfaces, plus UART, SPI, I2C, I3C, PWM, USB 2.0 and low-power GPIOs. Industrial variants add 1Gb Ethernet with IEEE 1588 TSN support and two CAN-FD interfaces, enabling deterministic networking and real-time industrial control for physical AI and robotics applications. In addition to the open-source Torq NPU compiler, the platform supports Zephyr RTOS.
Coralboard SR: putting the xMCU on the bench
The Coralboard SR development board is based on the new SR200 Series and was developed with Google Research. Across the SL and SR versions, the Coralboard family offers an edge AI developer experience delivered through the MLIR-based Synaptics Torq compiler and runtime, with open hardware and software for applications including wearables, hearables, smart home appliances, automation hubs, industrial control systems and robotics.
Model support is where the toolchain claim becomes concrete. According to Synaptics, the Torq open-source toolchain supports popular ML frameworks and is designed to provide day-0 support for edge AI model families such as Google Gemma3 270M, which achieves up to 12-16 tokens/second with INT8 and 4-bit quantization respectively, LiquidAI LFM2.5 and Ultralytics YOLO26. It uses active-research techniques such as batch-prefill and dynamic quantization.
Coralboard development board (Source: Synaptics Inc.)
Key features listed for the Coralboard SR:
- Astra SR250 Series with 800-MHz Arm Cortex M85 and Cortex M52
- 400 GOPS Torq/Coral NPU
- NOR flash memory and a microSD card slot
- integrated SRAM of up to 8 MB plus high-bandwidth custom DRAM of up to 256 MB
- Wi-Fi/Bluetooth connectivity, QWICC and mikroBUS connectors
- multi-camera and display support via CSI/DSI and USB, plus dual ISPs and digital mics
Coralboard SL: general availability and the specification sheet
Alongside the new board, Synaptics announced that the Coralboard SL is now generally available through DigiKey. It is powered by the Astra SL2619, which integrates the 1-TOPS Synaptics Torq NPU and is also the first implementation of the Coral NPU.
Its key features include the Astra SL2619 with 2× 2-GHz Arm Cortex A55 and Cortex-M52, a 1-TOPS Torq/Coral NPU, 2-GB DDR4, NOR flash memory, and add-on HATs for HDMI display, power, camera and digital mics. Like the Coralboard SR, it carries Wi-Fi/Bluetooth connectivity, QWICC and mikroBUS connectors, and multi-camera and display support via CSI/DSI and USB, as well as dual ISP and digital mic support.
| Attribute | Coralboard SR | Coralboard SL |
|---|---|---|
| Processor | Astra SR250 Series (xMCU) | Astra SL2619 |
| Host cores | 800-MHz Arm Cortex M85 + Cortex M52 | 2× 2-GHz Arm Cortex A55 + Cortex-M52 |
| Accelerator | 400 GOPS Torq/Coral NPU | 1-TOPS Torq/Coral NPU |
| Memory | SRAM up to 8 MB, custom DRAM up to 256 MB, NOR flash, microSD card slot | 2-GB DDR4, NOR flash |
| Expansion | Wi-Fi/Bluetooth, QWICC, mikroBUS, CSI/DSI, USB, dual ISPs, digital mics | Wi-Fi/Bluetooth, QWICC, mikroBUS, CSI/DSI, USB, add-on HATs for HDMI, power, camera, digital mics |
Orders for the Synaptics Coralboard run through DigiKey starting October 20, 2026.
FAQ: the questions product teams ask first
- What is an xMCU? It is Synaptics’ designation for a microcontroller class aimed at multimodal edge AI. The Astra SR200 series is its first family, and it differs from a conventional MCU by pairing heterogeneous compute and acceleration with integrated high-bandwidth custom DRAM.
- Which of the three versions fits a given design? The split is by throughput and I/O paths: SR210 at 200 GOPS for power-optimised, always-on voice and sensing; SR230 at 300 GOPS for vision, display and optional audio; SR250 at 400 GOPS for dual vision and display paths. All are pin-compatible within the xMCU series.
- Does the platform still need external memory? Synaptics says no for most applications: the custom DRAM scales to hundreds of megabytes and runs at one-third the power of typical system DRAM.
- What software stack is involved? An open-source MLIR/IREE compiler and the Torq NPU compiler, a shared SDK across the line-up, and Zephyr RTOS support, together with the MLIR-based Synaptics Torq compiler and runtime used on the boards.
- How are security requirements addressed? The SR200 Series meets PSA Level 3 and CC EAL4+ certification targets using a multi-layered security engine.
- What about industrial deployments? Industrial variants of the platform add 1Gb Ethernet with IEEE 1588 TSN support and two CAN-FD interfaces for deterministic, real-time control.
What to watch next
Two things will determine whether this launch reads as a category shift rather than another silicon refresh. The first is how far on-device multimodal inference actually travels in battery-powered products once the memory constraint is relaxed. The second is how quickly the open-source toolchain and the Coralboard family accumulate real developer usage — the combination of a pin-compatible xMCU series, day-0 model support and boards that reach the bench through DigiKey is the practical test of that adoption curve.
Written by David Nakamura, AI & Data News. Editorial contact: editorial@aidatanews.com.